Ann Kelleher On Future Technology

IEDM 2022 celebrated 75 Decades of the Transistor. I simply cannot imagine anything else invented in the final 75 several years has experienced as much impact on my existence, and possibly yours, much too.

After the awards session, the meeting got underway with a keynote by Ann Kelleher, Government Vice President and Normal Supervisor of Know-how Advancement at Intel. It was titled “Celebrating 75 Decades of the Transistor! A Appear In advance In direction of the Future Era of Innovation Prospects.”

I assume Ann has one of the most hard careers in the total semiconductor industry, illustrated by a single slide that she presented near the finish of her presentation:

You in all probability know that Intel was late with what it employed to phone 10nm and now calls Intel 7. It is now in higher-volume producing (HVM) and is pumping out Alder Lake, Raptor Lake, and Sapphire Rapids.

The subsequent technology course of action is Intel 4, which employed to be identified as 7nm. It is “manufacturing all set.” I’m not quite confident precisely what that suggests. It either is becoming utilised, or will be, to manufacture Meteor Lake. As I wrote in my post HOT CHIPS Working day 2: AI…and Much more Incredibly hot Chiplets, Meteor Lake is a 3D heterogeneous integration style and design:

This has a CPU tile, a GPU tile, an SoC tile, an I/O extender tile, and underneath it all, a foundation tile. Meteor Lake has been booted in the lab.

I assume just the CPU and GPU tiles are constructed in Intel 4.

Intel 3 ought to be all set in the 2nd fifty percent of following calendar year.

The upcoming procedure is Intel 20A (the A stands for Ångström), which is planned for the first 50 % of 2024 (to be made use of for Arrow Lake). This is a ribbon-FET (gate-all-around) approach.

Then Intel 18A is intended to be prepared in the second 50 percent of 2024 (possibly the method for Lunar Lake). This course of action is one particular that will be readily available to foundry consumers. This node is prepared to be the initial to use High-NA EUV if ASML can get it to operate by then (see my post What Is Higher-NA EUV?).

That is five method generations in a few or four several years (relying on in which you commence counting). I don’t imagine any firm has at any time tried to do anything so ambitious. Of training course, the next handful of years will convey to no matter if Intel succeeds at accomplishing this and “leapfrogging” the competitiveness. Some of this may just be naming. Intel 18A may well be an optical shrink of Intel 20A, alternatively than a true approach node.

Ann’s Keynote

Ann opened with her vital messages:

  • Moore’s Legislation is about innovation and is crucial to addressing computing need. Ok, that is a bit “motherhood and apple pie.”
  • Method-primarily based technological innovation co-optimization (STCO) is the up coming big evolution of innovation. This was presented as something manufacturer new, but it turns out my initial point out of STCO was in June 2018 in my post Imec Roadmap.
  • Challenges and alternatives are abundant and demand continued innovation throughout the whole ecosystem. This is what she put in a good deal of her presentation masking.

As I claimed over, 1 of her top-stage points is that the future belongs to STCO. Amongst other items, this signifies employing methods employing chiplets (which Intel typically calls “tiles”) and making use of Design and style Technological innovation Co-Optimization to enhance the design-procedure interface (things like bottom ability distribution or by means of pillars). Of system, there is a move to integrate the entire procedure, style and design the package, and manufacture it. Intel has two 3D packaging systems identified as Foveros and EMIB, and they occur in various flavors. Foveros Direct is a immediate copper-to-copper assembly approach.

STCO for a system starts off appropriate at the major with programs and workloads, and the software package load. This drives the procedure architecture at a higher amount, basically how to partition the structure into chiplets. In just the chiplets, there is foundational IP (conventional cells, reminiscences) but also core and accelerator IP (for foundry, Intel supports x86, Arm, and RISC-V). Ideal at the bottom is Ann’s area: transistors and interconnects, and the semiconductor processes used to manufacture them.

The middle aspect of Ann’s presentation was digging into a variety of areas and hunting at chances for the foreseeable future. There is a lot far too substantially to go over in a website article, so I’ll just checklist the matter locations:

  • People
  • Transistors
  • Interconnect
  • Resources
  • Reliability
  • Memory
  • Patterning
  • Software
  • Disaggregation
  • Producing
  • Advanced packaging

Immediately after covering the standing of the course of action roadmap (which I opened this submit with), Ann wrapped up with a glimpse of what exploration places Intel is operating on:

  • An added 10X improvement in density and placement overall flexibility for chiplet-centered designs.
  • Tremendous skinny elements to allow for scaling to go on (making use of 2D supplies for transistors at the time RibbonFET (GAA) operates out of steam).
  • New choices in electrical power effectiveness (GaN on silicon) and memory (FeRAM magneto-electric powered units).

Her very last slide was how Intel considers by itself to be the “steward of Moore’s Law”. Of class, Gordon Moore was a single of the founders of Intel, and its CEO from 1979 to 1987. Intel’s aspiration is for 1 trillion transistor models by 2030.

IEEE Spectrum interviewed Ann (I presume before she had given the keynote) and released its piece Intel’s Consider on the Upcoming Wave of Moore’s Law.